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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad711 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 precision, low cost, high speed, bifet op amp features enhanced replacement for lf411 and tl081 ac performance settles to 0.01% in 1.0 s 16 v/ s min slew rate (ad711j) 3 mhz min unity gain bandwidth (ad711j) dc performance 0.25 mv max offset voltage: (ad711c) 3 v/ c max drift: (ad711c) 200 v/mv min open-loop gain (ad711k) 4 v p-p max noise, 0.1 hz to 10 hz (ad711c) available in plastic mini-dip, plastic soic, hermetic cerdip, and hermetic metal can packages mil-std-883b parts available available in tape and reel in accordance with eia-481a standard surface mount (soic) dual version: ad712 product description the ad711 is a high speed, precision monolithic operational amplifier offering high performance at very modest prices. its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology. these performance benefits allow the user to easily upgrade existing designs that use older precision bifets and, in many cases, bipolar op amps. the superior ac and dc performance of this op amp makes it suitable for active filter applications. with a slew rate of 16 v/ m s and a settling time of 1 m s to 0.01%, the ad711 is ideal as a buffer for 12-bit d/a and a/d converters and as a high-speed integrator. the settling time is unmatched by any similar ic amplifier. the combination of excellent noise performance and low input current also make the ad711 useful for photo diode preamps. common-mode rejection of 88 db and open loop gain of 400 v/mv ensure 12-bit performance even in high-speed unity gain buffer circuits. the ad711 is pinned out in a standard op amp configuration and is available in seven performance grades. the ad711j and ad711k are rated over the commercial temperature range of 0 c to 70 c. the ad711a, ad711b and ad711c are rated over the industrial temperature range of ?0 c to +85 c. the ad711s and ad711t are rated over the military temperature range of ?0 c to +125 c and are available processed to mil- std-883b, rev. e. extended reliability plus screening is available, specified over the commercial and industrial temperature ranges. plus screening includes 168 hour burn-in, as well as other environ- mental and physical tests. the ad711 is available in an 8-pin plastic mini-dip, small outline, cerdip, to-99 metal can, or in chip form. product highlights 1. the ad711 offers excellent overall performance at very competitive prices. 2. analog devices?advanced processing technology and 100% testing guarantee a low input offset voltage (0.25 mv max, c grade, 2 mv max, j grade). input offset voltage is specified in the warmed-up condition. analog devices?laser wafer drift trimming process reduces input offset voltage drifts to 3 m v/ c max on the ad711c. 3. along with precision dc performance, the ad711 offers excellent dynamic response. it settles to 0.01% in 1 m s and has a 100% tested minimum slew rate of 16 v/ m s. thus this d evice is ideal for applications such as dac and adc buffers which require a combination of superior ac and dc performance. 4. the ad711 has a guaranteed and tested maximum voltage noise of 4 m v p-p, 0.1 to 10 hz (ad711c). 5. analog devices?well-matched, ion-implanted jfets ensure a guaranteed input bias current (at either input) of 25 pa max (ad711c) and an input offset current of 10 pa max (ad711c). both input bias current and input offset current are guaranteed in the warmed-up condition. connection diagrams 10k v os trim ?15v nc offset null inverting input non inverting input offset null output ?v s +v s nc = no connect ad711 note pin 4 connected to case 8 7 6 5 1 2 3 4 nc = no connect offset null nc output ad711 inverting input noninverting input ?v s +v s offset null
rev. e ? ad711?pecifications (v s = 15 v @ t a = 25 c, unless otherwise noted.) j/a/s k/b/t c parameter min typ max min typ max min typ max unit input offset voltage 1 initial offset 0.3 2/1/1 0.2 0.5 0.10 0.25 mv t min to t max 3/2/2 1.0 0.45 mv vs. temp 7 20/20/20 5 10 2 5 m v/ c vs. supply 76 95 80 100 86 110 db t min to t max 76/76/76 80 86 db long-term stability 15 15 15 m v/month input bias current 2 v cm = 0 v 15 50 15 50 15 25 pa v cm = 0 v @ t max 1.1/3.2/51 1.1/3.2/51 1.6 na v cm = 10 v 20 100 20 100 20 50 pa input offset current v cm = 0 v 10 25 5 25 5 10 pa v cm = 0 v @ t max 0.6/1.6/26 0.6/1.6/26 0.65 na frequency response small signal bandwidth 3.0 4.0 3.4 4.0 3.4 4.0 mhz full power response 200 200 200 khz slew rate 16 20 18 20 18 20 v/ m s settling time to 0.01% 1.0 1.2 1.0 1.2 1.0 1.2 m s total harmonic distortion 0.0003 0.0003 0.0003 % input impedance differential 3 10 12 5.5 3 10 12 5.5 3 10 12 5.5 w pf common mode 3 10 12 5.5 3 10 12 5.5 3 10 12 5.5 w pf input voltage range differential 3 20 20 20 v common-mode voltage 4 +14.5, ?1.5 +14.5, ?1.5 +14.5, ?1.5 t min to t max ? s + 4 +v s ?2 v s + 4 +v s ?2 v s + 4 +v ?2 v common-mode rejection ratio v cm = 10 v 76 88 80 8 88694db t min to t max 76/76/76 84 80 84 86 90 db v cm = 11 v 70 84 76 8 47690db t min to t max 70/70/70 80 74 80 74 84 db input voltage noise 2 2 2 4 m v p-p 45 45 45 nv/ hz 22 22 22 nv/ hz 18 18 18 nv/ hz 16 16 16 nv/ hz input current noise 0.01 0.01 0.01 pa/ hz open-loop gain 150 400 200 400 200 400 v/mv 100/100/100 100 100 v/mv output characteristics voltage +13, ?2.5 +13.9, ?3.3 +13, ?2.5 +13.9, ?3.3 +13, ?2.5 +13.9, ?3.3 v 12/ 12/ 12 +13.8, ?3.1 12 +13.8, ?3.1 12 +13.8, ?3.1 v current 25 25 25 ma power supply rated performance 15 15 15 v operating range 4.5 18 4.5 18 4.5 18 v quiescent current 2.5 3.4 2.5 3.0 2.5 2.8 ma notes 1 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = 25 c. 2 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = 25 c. for higher temperatures, the current doubles every 10 c. 3 defined as voltage between inputs, such that neither exceeds 10 v from ground. 4 typically exceeding ?4.1 v negative common-mode voltage on either input results in an output phase reversal. specifications subject to change without notice.
rev. e ad711 ? absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . . 500 mw input voltage 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v output short circuit duration . . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and ? s storage temperature range (q, h) . . . . . . . ?5 c to +150 c storage temperature range (n) . . . . . . . . . . ?5 c to +125 c operating temperature range ad711j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c ad711a/b/c . . . . . . . . . . . . . . . . . . . . . . . . ?0 c to +85 c ad711s/t . . . . . . . . . . . . . . . . . . . . . . . . . ?5 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 8-pin plastic package: q jc = 33 c/watt; q ja = 100 c/watt 8-pin cerdip package: q jc = 22 c/watt; q ja = 110 c/watt 8-pin metal can package: q jc = 65 c/watt; q ja = 150 c/watt 8-pin soic package: q jc = 43 c/watt; q ja = 160 c/watt 3 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. ordering guide temperature package package model range description option* * ad711ah ?0 c to +85 c 8-pin metal can h-08a ad711aq ?0 c to +85 c 8-pin ceramic dip q-8 * ad711bq ?0 c to +85 c 8-pin ceramic dip q-8 * ad711ch ?0 c to +85 c 8-pin metal can h-08a ad711jn 0 c to 70 c 8-pin plastic dip n-8 ad711jr 0 c to 70 c 8-pin plastic soic rn-8 ad711jr-reel 0 c to 70 c 8-pin plastic soic rn-8 ad711jr-reel7 0 c to 70 c 8-pin plastic soic rn-8 ad711kn 0 c to 70 c 8-pin plastic dip n-8 ad711kr 0 c to 70 c 8-pin plastic soic rn-8 ad711kr-reel 0 c to 70 c 8-pin plastic soic rn-8 ad711kr-reel7 0 c to 70 c 8-pin plastic soic rn-8 * ad711sq/883b ?5 c to +125 c 8-pin ceramic dip q-8 * ad711tq/883b ?5 c to +125 c 8-pin ceramic dip q-8 * not for new design, obsolete april 2002 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad711 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. e ad711typical performance characteristics ? supply voltage ? vo l t s output voltage swing ? volts 0 05 10 10 5 15 20 15 20 r l = 2k 25 c +v out ?v out tpc 2. output voltage swing vs. supply voltage temperature ? c input bias current (v cm = 0) ? amps 10 ?12 ?60 ?40 ?20 0 20 40 60 80 100 120 140 10 ?11 10 ?10 10 ?9 10 ?8 10 ?7 10 ?6 tpc 5. input bias current vs. tem- perature ambient temperature ? c short circuit current limit ? ma ?60 10 ?40 ?20 0 20 40 60 80 100 120 140 12 14 16 18 20 22 24 26 ?output current +output current tpc 8. short circuit current limit vs. temperature supply voltage ? vo l t s input voltage swing ? volts 0 05 10 10 5 15 20 15 20 r l = 2k 25 c tpc 1. input voltage swing vs. supply voltage supply voltage ? vo l t s qu iescent current ? ma 1.75 05 10 15 20 2.00 2.25 2.50 2.75 tpc 4. quiescent current vs. sup- ply voltage common mode voltage ? volts input bias current ? pa 0 ?10 50 25 75 100 max j grade limit ?5 0 5 10 v s = 15v 25 c tpc 7. input bias current vs. com- mon mode voltage load resistance ? output voltage swing ? volts p-p 0 10 15 100 1k 10k 20 25 30 10 5 15v supplies tpc 3. output voltage swing vs. load resistance frequency ? hz output impedance ? 0.01 1k a vcl = 1 10k 100k 1m 10m 0.01 1 10 100 tpc 6. output impedance vs. fre- quency temperature ? c unity gain bandwidtht ? mhz ?60 3.0 ?40 ?20 0 20 40 60 80 100 120 140 3.5 4.0 4.5 5.0 tpc 9. unity gain bandwidth vs. temperature
rev. e ? ad711 supply modulation frequency ? hz power supply rejection ? db 0 10 20 40 60 80 100 110 100 1k 10k 10k 1 ?supply +supply v s = 15 supplies with 1v p-p sine wa ve 25 c tpc 12. power supply rejection vs. frequency settling time ? s output swing frim 0v to vo l t s 0.5 ?10 ?8 ?6 ?4 ?2 0 2 2 4 6 8 0.6 0.7 0.8 0.9 1.0 error 1% 0.1% 0.01% 1% 0.1% 0.01% tpc 15. output swing and error vs. settling time input error signal ? mv (at summing junction) slew rate ? v s 0 0 100 200 300 400 5 10 15 20 25 500 600 700 800 900 tpc 18. slew rate vs. input error signal supply voltage ? vo l t s open-loop gain ? db 0 95 5101520 100 105 110 115 120 125 r l = 2k 25 c tpc 11. open-loop gain vs. supply voltage input frequency ? hz 0 5 10 30 10m 100k 1m 15 20 25 output voltage ? volts p-p r l = 2k 25 c v s = 15v tpc 14. large signal frequency response frequency ? hz 1 1 10 10 input noise voltage ? nv/ hz 100 1k 100 1k 10k 100k tpc 17. input noise voltage spectral density frequency ? hz open loop gain ? db 10 ?20 100 1k 10k 100k 1m 0 20 40 60 10m 80 100 gain r l = 2k c = 100pf phase ?20 0 20 40 60 80 100 phase margin ? degrees tpc 10. open-loop gain and phase margin vs. frequency frequency ? hz cmr ? db 100 0 10 20 100 v s = 15v v cm = 1v p-p 25 c 40 60 80 1k 10k 100k 1m tpc 13. common mode rejection vs. frequency frequency ? hz thd ? db ?130 100 ?120 ?110 ?100 ?90 ?80 ?70 1k 10k 100k 3v rms r l = 2k c l = 100pf tpc 16. total harmonic distor- tion vs. frequency
rev. e ad711 ? tpc 21. offset null configurations tpc 22c. unity gain follower pulse response (small signal) tpc 23c. unity gain inverter pulse response (small signal) tpc 20. t.h.d. test circuit tpc 22b. unity gain follower pulse response (large signal) tpc 23b. unity gain inverter pulse response (large signal) temperature ? c slew rate ? v/ s ?60 ?40 ?20 0 20 40 60 80 100 120 140 20 25 15 16 17 18 19 21 22 23 24 tpc 19. slew rate vs. temperature r l 2k v out v in +v s ?v s 0.1 f c l 100pf 0.1 f square wave input ad711 tpc 22a. unity gain follower r l 2k v out v in +v s ?v s 0.1 f c l 100pf 0.1 f square wave input 5k ad711 5k tpc 23a. unity gain inverter 2k output +v s ?v s 0.1 f 100pf 0.1 f ad711 input +v s ?v s 0.1 f ad711 10k 0.1 f 1.3mk +v s ?v s 0.1 f ad711 10k 0.1 f
rev. e ad711 ? optimizing settling time most bipolar high-speed d/a converters have current outputs; therefore, for most applications, an external op amp is required for current-to-voltage conversion. the settling time of the converter/op amp combination depends on the settling time of the dac and output amplifier. a good approximation is: t s total = ( t s dac ) 2 + ( t s amp ) 2 (1) the settling time of an op amp dac buffer will vary with the noise gain of the circuit, the dac output capacitance, and with the amount of external compensation capacitance across the dac output scaling resistor. settling time for a bipolar dac is typically 100 ns to 500 ns. previously, conventional op amps have required much longer settling times than have typical state-of-the-art dacs; therefore, the amplifier settling time has been the major limitation to a high-speed voltage-output d-to-a function. the introduction of the ad711/712 family of op amps with their 1 m s (to 0.01% of final value) settling time now permits the full high-speed capabilities of most modern dacs to be realized. in addition to a significant improvement in settling time, the low offset voltage, low offset voltage drift, and high open-loop gain of the ad711 family assures 12-bit accuracy over the full operating temperature range. the excellent high-speed performance of the ad711 is shown in the oscilloscope photos of figure 2. measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the ad711 ?both photos show the worst case situation: a full-scale input transition. the dac? 4 k w [10 k w 8 k w = 4.4 k w ] output impedance together with a 10 k w feedback resistor produce an op amp noise gain of 3.25. the current output from the dac produces a 10 v step at the op amp output (0 to ?0 v figure 2a, ?0 v to 0 v figure 2b.) therefore, with an ideal op amp, settling to 1/2 lsb ( 0.01%) requires that 375 m v or less appears at the summing junction. this means that the error between the input and output (that voltage which appears at the ad711 summing junction) must be less than 375 m v. as shown in figure 2, the total settling time for the ad711/ad565 combination is 1.2 microseconds. output ?10v to +10v +15v 0.1 f 10pf 0.1 f ad711k dac i out = 4 i ref code 0.5ma i ref 20k 19.95k r1 100 bipolar offset adjust i o dac out 10v span ?15v 20v span 5k 5k 5k 10v msb lsb ref out v cc ref in ref gnd r2 100 gain adjust 0.1 f ad565a bipolar off 9.95k ?v ee 0.1 f power gnd figure 1. 10 v voltage output bipolar dac figure 2. settling characteristics for ad711 with ad565a a. (full-scale negative transition) b. (full-scale positive transition)
rev. e ad711 ? op amp settling time? mathematical model the design of the ad711 gives careful attention to optimizing individual circuit components; in addition, a careful tradeoff was made: the gain bandwidth product (4 mhz) and slew rate (20 v/ m s) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore stability). thus designed, the ad711 settles to 0.01%, with a 10 v output step, in under 1 m s, while retaining the ability to drive a 100 pf load capacitance when operating as a unity gain follower. if an op amp is modeled as an ideal integrator with a unity gain crossover frequency of w o /2 p, equation 1 will accurately describe the small signal behavior of the circuit of figure 3a, consisting of an op amp connected as an i-to-v converter at the output of a bipolar or cmos dac. this equation would completely describe the output of the system if not for the op amp? finite slew rate and other nonlinear effects. v o i in = r r ( c f = c x ) w o s 2 + g n w o + rc f ? ? ? s + 1 (3) where: w o 2 p =op amp? unity gain frequency g n = ?oise?gain of circuit 1 + r r o ? ? ? this equation may then be solved for c f : c f = 2 - g n r w o + 2 rc x w o + (1 - g n ) r w o (3) in these equations, capacitor c x is the total capacitor appearing the inverting terminal of the op amp. when modeling a dac buffer application, the norton equivalent circuit of figure 3a can be used directly; capacitance c x is the total capacitance of the output of the dac plus the input capacitance of the op amp (since the two are in parallel). ad711 c x r o i o c f r r l c l v out figure 3a. simplified model of the ad711 used as a current-out dac buffer when r o and i o are replaced with their thevenin v in and r in equivalents, the general purpose inverting amplifier of figure 26b is created. note that when using this general model, capacitance c x is either the input capacitance of the op amp if a simple inverting op amp is being simulated or it is the combined capacitance of the dac output and the op amp input if the dac buffer is being modeled. ad711 c x r in c f r r l c l v out v in figure 3b. simplified model of the ad711 used as an inverter in either case, the capacitance c x causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp output. since the value of c x can be estimated with reasonable accuracy, equation 2 can be used to choose a small capacitor, c f , to cancel the input pole and optimize amplifier response. figure 4 is a graphical solution of equation 2 for the ad711 with r = 4 k w . c f 0 0 10 c x 10 20 30 40 50 60 20 30 40 50 60 g n = 4.0 g n = 1.0 g n = 1.5 g n = 2.0 g n = 3.0 figure 4. value of capacitor c f vs. value of c x the photos of figures 5a and 5b show the dynamic response of the ad711 in the settling test circuit of figure 6. the input of the settling time fixture is driven by a flat-top pulse generator. the error signal output from the false summing node of a1 is clamped, amplified by a2 and then clamped again. the error signal is thus clamped twice: once to prevent overloading amplifier a2 and then a second time to avoid overloading the oscilloscope preamp. the tektronix oscilloscope preamp type 7a26 was carefully chosen because it does not overload with these input levels. amplifier a2 needs to be a very high speed fet-input op amp; it provides a gain of 10, amplifying the error signal output of a1.
rev. e ad711 ? figure 5a. settling characteristics 0 to +10 v step upper trace: output of ad711 under test (5 v/div) lower trace: amplified error voltage (0.01%/div) figure 5b. settling characteristics 0 to ?0 v step upper trace: output of ad711 under test (5 v/div) lower trace: amplified error voltage (0.01%/div) guarding the low input bias current (15 pa) and low noise characteristics of the ad711 bifet op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere 5pf ad3554 v error 5 +15v 5k ?15v 0.47 f hp2835 textronix 7a26 oscilloscope preamp input selection 1m 20pf 0.1 f ad711 +15v ?15v 0.1 f v out 10pf hp2835 10k 0.2-0.0pf 1.1k 10k 5-18pf 10k 200k 4.99k 4.99k v in data d ynamics 5109 (or equivalent flat top pulse generator) 0.47 f 205 figure 6. settling time test circuit current-to-voltage converters. the use of a guarding technique such as that shown in figure 7, in printed circuit board layout and construction is critical to minimize leakage currents. the guard ring is connected to a low impedance potential at the same level as the inputs. high impedance signal lines should not be extended for any unnecessary length on the printed circuit board. 1 8 7 6 5 4 3 2 6 5 7 8 2 3 1 4 figure 7. board layout for guarding inputs d/a converter applications the ad711 is an excellent output amplifier for cmos dacs. it can be used to perform both 2-quadrant and 4-quadrant operation. the output impedance of a dac using an inverted r-2r ladder approaches r for codes containing many 1s, 3r for codes containing a single 1, and for codes containing all zero, the output impedance is infinite. for example, the output resistance of the ad7545 will modu- late between 11 k w and 33 k w . therefore, with the dac? internal feedback resistance of 11 k w , the noise gain will vary from 2 to 4/3. this changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear dac amplifier performance. the ad711k with guaranteed 500 m v offset voltage minimizes this effect to achieve 12-bit performance.
rev. e ad711 ?0 ad711k c f v out 0.1 f 0.1 f ?15 +15 c1 33pf r2 * out1 r fb v dd v ref dgnd agnd r1 * v in analog common gain adjust db11-db0 v dd ad7545 * for values r1 and r2, refer to table 1 figure 8. unipolar binary operation r1 and r2 calibrate the zero offset and gain error of the dac. specific values for these resistors depend upon the grade of ad7545 and are shown below. table i. recommended trim resistor values vs. grades of the ad7545 for v dd = 5 v trim resistor jn/aq/sd kn/bq/td ln/cq/ud gln/gcq/gud r1 500 w 200 w 100 w 20 w r2 150 w 68 w 33 w 6.8 w noise characteristics the random nature of noise, particularly in the 1/f region, makes it difficult to specify in practical terms. at the same time, designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their equipment. the ad711c grade is specified at a maximum level of 4.0 m v p-p, in a 0.1 hz to 10 hz bandwidth. each ad711c receives a 100% noise test for two 10-second intervals; devices with any excursion in excess of 4.0 m v are rejected. the screened lot is then submitted to quality control for verification on an aql basis. all other grades of the ad711 are sample-tested on an aql basis to a limit of 6 m v p-p, 0.1 to 10 hz. driving the analog input of an a/d converter an op amp driving the analog input of an a/d converter, such as that shown in figure 11, must be capable of maintaining a constant output voltage under dynamically changing load conditions. in successive-approximation converters, the input current is compared to a series of switched trial currents. the comparison point is diode clamped but may deviate several hundred millivolts resulting in high frequency modulation of a/d input current. figures 10a and 10b show the settling time characteristics of the ad711 when used as a dac output buffer for the ad7545. a. full-scale positive b. full-scale negative transition transition figure 10. settling characteristics for ad711 with ad7545 compared to a series of switched trial currents. the comparison point is diode clamped but may deviate several hundred milli- volts resulting in high frequency modulation of a/d input current. the output impedance of a feedback amplifier is made artificially low by the loop gain. at high frequencies, where the loop gain is low, the amplifier output impedance can approach its open loop value. most ic amplifiers exhibit a minimum open loop output impedance of 25 w due to current limiting resistors. a few hundred microamps reflected from the change in con- verter loading can introduce errors in instantaneous input figures 8 and 9 show the ad711 and ad7545 (12-bit cmos dac) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. capacitor c1 provides phase compensation to reduce overshoot and ringing. +15v 0.1 f 0.1 f ad711k ?15v r3 10k 1% +15v 0.1 f 0.1 f ad711k ?15v r5 20k 1% r4 20k 1% r2 * c1 33pf out1 r fb v dd v ref dgnd agnd r1 * v in gain adjust db11-db0 v dd v out ad7545 12 da ta input analog common * for values r1 and r2, refer to table 1 figure 9. bipolar operation +15v 0.1 f 0.1 f ad711 ?15v r2 100 gain adjust 12/ 8 r1 100 offset adjust cs a o r/ c ce ref in ref out bip off 10v in 20v in ana com sts high bits middle bits low bits +5v +15v ?15v dig com ad574 10v analog input analog com figure 11. ad711 as adc unity gain buffer
rev. e ad711 ?1 driving a large capacitive load the circuit in figure 13 employs a 100 w isolation resistor which enables the amplifier to drive capacitive loads exceeding 1500 pf; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. low frequency feedback is returned to the amplifier summing junction via the low pass filter formed by the 100 w series resistor and the load capaci- tance, c l . figure 14 shows a typical transient response for this connection. r l input +v s ?v s 0.1 f c l 0.1 f typical capacitance limit for various load resistors r l c l up to 2k 1500pf 10k 1500pf 20k 1000pf 4.99k ad711 100 30pf 4.99k output figure 13. circuit for driving a large capacitive load figure 14. transient response r l = 2 k w , c l = 500 pf active filter applications in active filter applications using op amps, the dc accuracy of the amplifier is critical to optimal filter performance. the amplifier? offset voltage and bias current contribute to output error. offset voltage will be passed by the filter and may be amplified to produce excessive output offset. for low frequency applications requiring large value input resistors, bias currents flowing through these resistors will also generate an offset voltage. in addition, at higher frequencies, an op amp? dynamics must be carefully considered. here, slew rate, bandwidth, and open-loop gain play a major role in op amp selection. the slew rate must be fast as well as symmetrical to minimize distortion. the amplifier? bandwidth in conjunction with the filter? gain will dictate the frequency response of the filter. the use of a high performance amplifier such a s the ad711 will minimize both dc and ac errors in all active filter applica- tions. second order low pass filter figure 15 depicts the ad711 configured as a second order butterworth low pass filter. with the values as shown, the corner frequency will be 20 khz; however, the wide bandwidth of the ad711 permits a corner frequency as high as several hundred kilohertz. equations for component selection are shown below. r 1 = r 2 = user selected ( typical values : 10 k w ?100 k w ) (4) c 1 = 1. 414 (2 p )( f cutoff )( r 1) , c 2 = 0. 707 (2 p )( f cutoff )( r 1) (5) where: c1 and c2 are in farads. v out +15v ?15v 0.1 f 0.1 f ad711 v in c2 280pf r2 20k r1 20k c1 560pf figure 15. second order low pass filter an important property of filters is their out-of-band rejection. the simple 20 khz low pass filter shown in figure 15, might be used to condition a signal contaminated with clock pulses or sampling glitches which have considerable energy content at high frequencies. the low output impedance and high bandwidth of the ad711 minimize high frequency feedthrough as shown in figure 16. the upper trace is that of another low-cost bifet op amp showing 17 db more feedthrough at 5 mhz. figure 16. voltage. if the a/d conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier? output will return to the nominal value before the converter makes its comparison. however, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. the ad711 is ideally suited to drive high speed a/d converters since it offers both wide bandwidth and high open-loop gain. a. source current = 2 ma b. sink current = 1 ma figure 12. adc input unity gain buffer recovery times
rev. e ad711 ?2 +15v ?15v 0.1 f 0.1 f a1 ad711 v in v out +15v ?15v 0.1 f 0.1 f a2 ad711 a * b * c * d * 0.001 f 4.9395e ?15 5.9276e ?15 5.9276e ?15 4.9395e ?15 2800 6190 6490 6190 0.001 f 100k 124k 2800 * see text 4.99k 4.99k figure 17. 9-pole chebychev filter +15v ?15v 0.1 f 0.1 f 1/2 ad712 1/2 ad712 0.001 f 0.001 f r 1k 4.99k r: 24.9k for 4.9395e ?15 29.4k for 5.9276e ?15 figure 18. fdnr for 9-pole chebychev filter figure 19. high frequency response for 9-pole chebychev filter 9-pole chebychev filter figure 17 shows the ad711 and its dual counterpart, the ad712, as a 9-pole chebychev filter using active frequency dependent negative resistors (fdnr). with a cutoff frequency of 50 khz and better than 90 db rejection, it may be used as an anti-aliasing filter for a 12-bit data acquisition system with 100 khz throughput. as shown in figure 17, the filter is comprised of four fdnrs (a, b, c, d) having values of 4.9395 10 ?5 and 5.9276 10 ?5 farad-seconds. each fdnr active network provides a 2-pole response; for a total of 8 poles. the 9th pole consists of a 0.001 m f capacitor and a 124 k w resistor at pin 3 of amplifier a2. figure 18 depicts the circuits for each fdnr with the proper selection of r. to achieve optimal performance, the 0.001 m f capacitors must be selected for 1% or better matching and all resistors should have 1% or better tolerance.
rev. e ad711 ?3 outline dimensions 8-lead metal can [to-99] (h-8) dimensions shown in inches and (millimeters) 0.2500 (6.35) min 0.5000 (12.70) min 0.1850 (4.70) 0.1650 (4.19) reference plane 0.0500 (1.27) max 0.0190 (0.48) 0.0160 (0.41) 0.0210 (0.53) 0.0160 (0.41) 0.0400 (1.02) 0.0100 (0.25) 0.0400 (1.02) max base & seating plane 0.0340 (0.86) 0.0280 (0.71) 0.0450 (1.14) 0.0270 (0.69) 0.1600 (4.06) 0.1400 (3.56) 0.1000 (2.54) bsc 6 2 8 7 5 4 3 1 0.2000 (5.08) bsc 0.1000 (2.54) bsc 45 bsc 0.3700 (9.40) 0.3350 (8.51) 0.3350 (8.51) 0.3050 (7.75) controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-002ak 8-lead ceramic dip ?glass hermetic seal [cerdip] (q-8) dimensions shown in inches and (millimeters) 1 4 85 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inch; millimeters dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design 8-lead plastic dual-in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeters dimensions (in parentheses) compliant to jedec standards mo-095aa 8-lead standard small outline package [soic] narrow body (rn-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa
rev. e ad711 ?4 revision history location page 10/02?ata sheet changed from rev. d to rev. e. edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 10/02?ata sheet changed from rev. c to rev. d. edits to connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5/02?ata sheet changed from rev. b to rev. c. change from small outline package (r-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 deleted metallization photograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
?5
?6 c00832??0/02(e) printed in u.s.a.

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